1. Field of the Invention
The present invention relates to the use of codes for error detection and/or error correction within a computer system. More specifically, the present invention relates to a method and an apparatus for updating an error-correcting code and/or an error-detecting code for a line when only a portion of the line is updated.
2. Related Art
As computer system memories continue to grow in size, it is becoming increasingly more common for transient errors to arise within the large volumes of code and/or data that are stored in these memories.
In order to remedy this problem, computer systems often employ error-correcting codes to correct transient errors that occur in a memory. When a data word is stored into the memory, the system automatically computes an error-correcting code for the data word that is stored along with the data word in the memory. When the data word is subsequently read from the memory, it is automatically compared against the error-correcting code. If a minor error has occurred, the error can be corrected through use of the error-correcting code. For example, a Hamming code can be used to correct any single-bit error and to detect any double-bit error occurring within a data word. See “Computer Organization and Architecture,” by William Stallings, Macmillan Publishing Company, 1987, pp. 99-106.
However, such error-correcting codes have typically been deployed in the slower semiconductor main memory of a computer system. It has proven much harder to employ such error-correcting codes in faster cache memories.
FIG. 1A illustrates how cache memories can be organized in a multiprocessor system. This multiprocessor system includes a number of processors 151-154 with associated level one (L1) caches, 161-164, that share a single level two (L2) cache 180 and a memory 183 (see FIG. 1). During operation, if a processor 151 accesses a data item that is not present in its local L1 cache 161, the system attempts to retrieve the data item from L2 cache 180. If the data item is not present in L2 cache 180, the system first retrieves the data item from memory 183 into L2 cache 180, and then from L2 cache 180 into L1 cache 161.
As computer system performance continues to increase, it is advantageous for L1 caches 161-164 to be organized as “write-through” caches, so that all updates the L1 caches 161-164 are automatically propagated to L2 cache 180. This makes all updates to L1 caches 161-164 visible in L2 cache 180, and thereby eliminates the need to retrieve a cache line from one of the L1 caches 161-164 in order to update the cache line.
Unfortunately, the frequent updates to L2 cache 180 can cause performance problems, especially if L2 cache employs error-correcting codes. If an update is a “partial store” that modifies only a portion of a data word in L2 cache 180, the data word must first be read out from L2 cache and then modified before the new error-correcting code can be computed. Hence, both a read operation and a subsequent write operation are required to update the error-correcting code. This can cause serious performance problems if L2 cache 180 is continually receiving such updates from the multiple L1 caches 161-164. (Note that the data word size for error-correcting code purposes is not necessarily the same as the data word size for the processor. For example, the data word size for error-correcting code purposes may be 256 bits, while the data word size for the processor architecture is 64 bits.)
Hence, what is needed is a method and an apparatus for updating an error-correcting code within a cache during a partial store operation without having to perform separate read and write operations.